Obsidian: Pattern-Based Unit Test Implementations

Test Pattern Generation Using a Dual MAC Unit

BIST (built-in self test) is one of the most attractive solutions to test chips at speed. In this paper, we present a new test pattern generation method using the processing units of DSP (digital signal processing). This method utilizes dual MAC (multiply and accumulate) units, which consist of two multipliers and several accumulators, in DSP to generate test patterns. The proposed test pattern...

Improving Security For Elliptic Curve Implementations on Smart Cards: A Random Number Generator Test Unit

Towards Automated Unit Testing of Statechart Implementations

This report describes an automated method of unit test design based on requirements speciied in a subset of the statechart notation. The behaviour under test is rst extracted from the requirements and speciied in the Z notation. Existing methods and tools are then applied to this speciication to derive the tests. Using Z to model the requirements and specify the tests allows for a deductive app...

Analogue Core-Based Test-Pattern Generation*

– Core-based testing, which is described by the proposed IEEE standard P1500, is an effective test method for Systems-on-Chip (SOC) containing embedded cores. This test method is usable for all classes of digital cores and provides solutions that allow automatic identification and configuration of testability features in SOC containing embedded cores. In this moment, IEEE P1500 is restricted to...

SAT-based Automatic Test Pattern Generation

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for Automatic Test Pattern Generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on Conjunctive Normal Forms (CNF), the problem has to be transformed. During transformati...